Design, Automation and Test in Europe Conference |
The Design, Automation, and Test in Europe (DATE) Conference and Exhibition is an annual event, scheduled in 2020 to be held March 9–13, 2020, at the Alpexpo Congress Centre in Grenoble. Because of the COVID-19 outbreak, the conference took place in a virtual environment, in April and May 2020.
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The DATE 2020 Conference and Exhibition was initially planned to take place in Grenoble, France from 9 to 13 March 2020. Due to the growing impact of the worldwide COVID-19 pandemic, the Organising Committees decided to transform the physical event in Grenoble to a virtual event online – an effectful decision which received great support from speakers who contributed presentations of high-quality on short notice to make sure that if participants cannot come to DATE, DATE comes to participants.
DATE combines the world’s favourite electronic systems design and test conference with an international exhibition for electronic design, automation and test, from system-level hardware and software implementation right down to integrated circuit design. This year, the conference was held as a virtual event from April to June 2020.
The virtual event mostly followed the initially planned programme of the physical event. Solely the seven in-depth technical tutorials could not be realised via the online platform.
The virtual Opening Ceremony of DATE 2020 included the first plenary keynote lecture by Luca Benini, ETH Zurich (Switzerland), who provided his presentation on the topic of “Open Parallel Ultra-Low Power Platforms for Extreme Edge AI”.
Catherine Schuman, Oak Ridge National Laboratory (US) focussed her Tuesday Lunchtime Keynote on Neuromorphic Computing and allowed participants to inspect challenges in that area also in relation to challenges in systems design.
The main conference programme from Tuesday to Thursday included 58 technical sessions organized in parallel tracks from the four areas
D – Design Methods & Tools
A – Application Design
T – Test and Dependability
E – Embedded and Cyber-physical Systems
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The 24th DATE conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors as well as specialists in hardware and software design, test and manufacturing of electronic circuits and systems. DATE puts strong emphasis on both technology and systems, covering ICs/SoCs, emerging technologies, embedded systems and embedded software.
The five-day event consists of a conference with plenary invited papers, regular papers, panels, hot-topic sessions, tutorials, workshops, special focus days and a track for executives. The scientific conference is complemented by a commercial exhibition showing the state-of-the-art in design and test tools, methodologies, IP and design services, reconfigurable and other hardware platforms, embedded software and (industrial) design experiences from different application domains, such as automotive, wireless, telecom and multimedia applications. The organisation of user group meetings, fringe meetings, a university booth, a PhD forum, vendor presentations and social events offers a wide variety of extra opportunities to meet and exchange information on relevant issues for the design automation, design and test communities. Special space will also be allocated for EU-funded projects to show their results.
More details are available on the DATE website: www.date-conference.com.
Within the scope of the conference, the main areas of interest are: design automation, design tools and hardware architectures for electronic and embedded systems; test and dependability at system, chip, circuit and device level for analogue and digital electronics; modelling, analysis, design and deployment of embedded software and cyber-physical systems; application design and industrial design experiences.
Topics of interest include, but are not restricted to:
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All papers have to be submitted electronically by Monday, 14 September 2020, as abstracts and by Monday, 21 September 2020 as full papers via: www.date-conference.com
Papers can be submitted either for standard oral presentation or for interactive presentation.
The Program Committee also encourages proposals for Special Sessions, Tutorials, Friday Workshops, University Booth Demonstrations, PhD Forum and Exhibition Theatre.
ChairsGeneral Chair: Programme Chair: |
Conference Organisationc/o K.I.T. Group GmbH Dresden |
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Alireza Mahzoon, University of Bremen, DE
is awarded for the presentation
Proving Correctness of Industrial Multipliers using Symbolic Computer Algebra
Behnaz Pourmohseni, Friedrich Alexander Universität Erlangen Nürnberg (FAU), DE
is awarded for the work
System-Level Mapping, Analysis, and Management of Real-Time Applications in Many-Core Systems
The 2020 EDAA Achievement Award ceremony by Norbert Wehn starts in the video below.
Luca Benini, ETHZ, Switzerland
https://www.edaa.com/press_releases/PR_achievement_2020_results.pdf
The EDAA Outstanding Dissertations Award 2019 ceremony by Lorena Anghel starts in the video below.
Eric Schneider, Ph.D
Multi-Level Simulation of Nano-Electronic Digital Circuits on GPUs
Fabio Passos, Ph.D.
A Multilevel Approach to the Systematic Design of Radio-Frequency Integrated Circuits
Ahmedullah Aziz, Ph.D.
Device-Circuit Co-design Employing Phase Transition Materials for Low Power Electronics
Innocent Agbo, Ph.D.
Reliability Modeling and Mitigation for Embedded Memories
Alwin Zulehner, Ph.D.
Design Automation for Quantum Computing
https://www.edaa.com/press_releases/EDAA_Award_2019_Results.pdf
The DATE Fellow Award ceremony by Norbert Wehn starts in the video below at minute 2:50.
Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE
Jan Madsen, Technical University of Denmark, DK
Giorgio Di Natale, CNRS/TIMA, FR
The Best Paper Award ceremony by Cristiana Bolchini during her opening talk video below starts at minute 2:05.
Each year the Design, Automation and Test in Europe Conference presents awards to the authors of the best papers. The selection is performed by the award committee composed of the Track Chairs Cristiana Bolchini, Theocharis Theocharides, Jaume Abella and Valeria Bertacco and the following members: Borzoo Bonakdarpour, Andrea Calimera, Ramon Canal, Luca Carloni, Alessandro Cimatti, Ayse Coskun, Nikil Dutt, Ioannis Papaefstathiou, Dionisios Pnevmatikatos, Davide Quaglia, Muhammad Shafique, Olivier Sentieys, Luis Miguel Silveira, Juergen Teich, Vasileios Tenentes, Jerzy Tyszer, Arnaud Virazel.
Impact of Magnetic Coupling and Density on STT-MRAM Performance
Lizhou Wu1, Siddharth Rao2, Mottaqiallah Taouil1, Erik Jan Marinissen2, Gouri Sankar Kar2 and Said Hamdioui1
1TU Delft, NL; 2IMEC, BE
A Flexible and Scalable NTT Hardware: Applications from Homomorphically Encrypted Deep Learning to Post-Quantum Cryptography
Ahmet Can Mert1, Emre Karabulut2, Erdinc Ozturk1, Erkay Savas1, Michela Becchi2 and Aydin Aysu2
1Sabanci University, TR; 2North Carolina State University, US
DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic Search
Ioannis Tsiokanos1, Lev Mukhanov1, Giorgis Georgakoudis2, Dimitrios S. Nikolopoulos3 and Georgios Karakonstantis1
1Queen's University Belfast, GB; 2Lawrence Livermore National Laboratory, US; 3Virginia Tech, US
Statistical Time-based Intrusion Detection in Embedded Systems
Nadir Carreon Rascon, Allison Gilbreath and Roman Lysecky
University of Arizona, US
Fast and Accurate DRAM Simulation: Can we Further Accelerate it?
Johannes Feldmann1; Matthias Jung2; Kira Kraft1; Lukas Steiner1; Norbert Wehn1
1TU Kaiserslautern, 2Fraunhofer IESE
ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning
Davide Giri; Kuan-Lin Chiu; Giuseppe Di Guglielmo; Paolo Mantovani; Luca Carloni
Columbia University
Verification Runtime Analysis: Get the Most Out of Partial Verification
Martin Ring1; Fritjof Bornbebusch1; Christoph Lüth1,2; Robert Wille3; Rolf Drechsler1,2
1DFKI, 2University of Bremen, 3Johannes Kepler University Linz
Gap-free Processor Verification by S²QED and Property Generation
Keerthikumara Devarajegowda1; Mohammad Rahmani Fadiheh2; Eshan Singh3; Clark Barrett3; Subhasish Mitra3; Wolfgang Ecker1; Dominik Stoffel2; Wolfgang Kunz2
1Infineon Technologies, 2TU Kaiserslautern, 3Stanford University
GANA: Graph Convolutional Network Based Automated Netlist Annotation
for Analog Circuits
Kishor Kunal1; Tonmoy Dhar1; Meghna Madhusudan1; Jitesh Poojary1; Arvind Sharma1; Wenbin Xu2; Steven Burns3; Jiang Hu2; Ramesh Harjani1; Sachin S. Sapatnekar1
1University of Minnesota, 2Texas A&M University, 3Intel Corporation
Backtracking Search for Optimal Parameters of a PLL-based True Random Number Generator
Brice Colombier; Nathalie Bochard; Florent Bernard; Lilian Bossuet
University of Lyon
GRAMARCH: A GPU-ReRAM based Heterogeneous Architecture
for Neural Image Segmentation
Biresh Kumar Joardar1; Nitthilan Kannappan Jayakodi1; Jana Doppa1; Partha Pratim Pande1; Hai (Helen) Li2; Krishnendu Chakrabarty3
1Washington State University, 2Duke University/TUM-IAS, 3Duke University
PSB-RNN: A Processing-in-Memory Systolic Array Architecture
using Block Circulant Matrices for Recurrent Neural Networks
Nagadastagiri1; Sahithi Rampalli1; Makesh Tarun Chandran1; Gurpreet Singh Kalsi2; John (Jack) Sampson1; Sreenivas Subramoney2; Vijaykrishnan Narayanan1
1The Pennsylvania State University, 2Processor Architecture Research Lab, Intel Labs
A Learning-Based Thermal Simulation Framework
for Emerging Two-Phase Cooling Technologies
Zihao Yuan1; Geoffrey Vaartstra2; Prachi Shukla1; Zhengmao Lu2; Evelyn Wang2; Sherief Reda3; Ayse Coskun1
1Boston University, 2Massachusetts Institute of Technology, 3Brown University
ProxSim: Simulation Framework for Cross-Layer Approximate DNN Optimization
Cecilia De la Parra1; Andre Guntoro1; Akash Kumar2
1Robert Bosch GmbH, 2TU Dresden
A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs
Ankita Nayak; Keyi Zhang; Raj Setaluri; Alex Carsello; Makai Mann; Stephen Richardson; Rick Bahr; Pat Hanrahan; Mark Horowitz; Priyanka Raina
Stanford University
Floating Random Walk Based Capacitance Solver for VLSI Structures
with Non-Stratified Dielectrics
Mingye Song; Ming Yang; Wenjian Yu
Tsinghua University
Ternary Compute-Enabled Memory based on Ferroelectric Transistors
for Accelerating Deep Neural Networks
Sandeep Krishna Thirumala; Shubham Jain; Sumeet Gupta; Anand Raghunathan
Purdue University
Impact of Magnetic Coupling and Density on STT-MRAM Performance
Lizhou Wu1; Siddharth Rao2; Mottaqiallah Taouil1; Erik Jan Marinissen2;
Gouri Sankar Kar2; Said Hamdioui1
1Delft University of Technology, 2IMEC
GenieHD: Efficient DNA Pattern Matching Accelerator Using Hyperdimensional Computing
Yeseong Kim; Mohsen Imani; Niema Moshiri;Tajana Rosing
University of California San Diego
Achieving Determinism in Adaptive AUTOSAR
Christian Menard1; Andres Goens1; Marten Lohstroh2; Jeronimo Castrillon1
1TU Dresden, 2University of California, Berkeley
A Flexible and Scalable NTT Hardware: Applications from Homomorphically Encrypted Deep Learning to Post-Quantum Cryptography
Ahmet Can Mert1; Emre Karabulut2; Erdinc Ozturk1; Erkay Savas1;
Michela Becchi2; Aydin Aysu2
1Sabanci University, 2North Carolina State University
AntiDOte: Attention-based Dynamic Optimization for Neural Network Runtime Efficiency
Fuxun Yu1; Chenchen Liu2; Di Wang3; Yanzhi Wang1; Xiang Chen1
1George Mason University, 2University of Maryland, 3Microsoft
Go Unary: A Novel Synapse Coding and Mapping Scheme
for Reliable ReRAM-based Neuromorphic Computing
Chang Ma; Yanan Sun; Weikang Qian; Ziqi Meng; Rui Yang; Li Jiang
Shanghai Jiao Tong University
On Improving Fault Tolerance of Memristor Crossbar Based Neural Network Designs
by Target Sparsifying
Song Jin1; Songwei Pei2; Yu Wang1
1North China Electric Power University,
2Beijing University of Posts and Telecommunications
Synthesis of Fault-Tolerant Reconfigurable Scan Networks
Sebastian Brandhofer; Michael Kochte; Hans-Joachim Wunderlich
University of Stuttgart
DEFCON: Generating and Detecting Failure-prone Instruction Sequences
via Stochastic Search
Ioannis Tsiokanos1; Lev Mukhanov2; Giorgis Georgakoudis3;
Dimitrios S. Nikolopoulos4; Georgios Karakonstantis1
1Queen's University Belfast, 2QUB, 3Lawrence Livermore National Laboratory,
4Virginia Tech
Thermal-Cycling-aware Dynamic Reliability Management in Many-Core System-on-Chip
Mohammad-Hashem Haghbayan1; Antonio Miele2; Zhuo Zou3;
Hannu Tenhunen1; Juha Plosila1
1University of Turku, 2Politecnico di Milano,
3Nanjing University of Computer Science and Technology
Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks
Byungmin Ahn; Taewhan Kim
Seoul National University
ACOUSTIC: Accelerating Convolutional Neural Networks
through Or-Unipolar Skipped Stochastic Computing
Wojciech Romaszkan; Tianmu Li; Tristan Melton; Sudhakar Pamarti; Puneet Gupta
University of California Los Angeles
Statistical Time-based Intrusion Detection in Embedded Systems
Nadir Carreon Rascon; Allison Gilbreath; Roman Lysecky
University of Arizona
Energy-efficient runtime resource management for adaptable multi-application mapping
Robert Khasanov; Jeronimo Castrillon
TU Dresden
CPS-oriented Modeling and Control of Traffic Signals Using Adaptive Back Pressure
Wanli Chang1; Debayan Roy2; Shuai Zhao1; Anuradha Annaswamy3; Samarjit Chakraborty2
1University of York, 2Technical University of Munich,
3Massachusetts Institute of Technology
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***Update May 2020: The virtual conference platform deadline is extended to 30 June 2020.***
For the last weeks, the DATE Committees have been working intensively to transform DATE 2020 into a virtual conference. More than 400 presentations were submitted. Again, we would like to express our deepest gratitude to all presenters for their contributions, despite the demanding situation worldwide, as well as participants for their patience. We would also like to thank all exhibitors and sponsors for their ongoing support.
We are glad to announce that the virtual conference has now been launched and can be accessed via www.date-conference-virtual.com.
All participants received an invitiation link to generate their personal log-in data via e-mail this morning.
Once you created your log-in you can view the virtual conference in accordance with your initial conference registration.
The platform will remain open until 31 May 2020 to ensure that you will be able to view the fascinating presentations.
If you have any questions regarding the virtual conference, please do not hesitate to contact the DATE Conference Registration under date-registration
kitdresden [dot] de (date-registration[at]kitdresden[dot]de)!
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***Update 14 April 2020: The virtual conference platform will be launched shortly. Participants may expect further information as well as access data via e-mail in the course of the week.***
The Corona virus (COVID-19) is affecting the plans of many people who made arrangements to attend DATE 2020 in Grenoble. The DATE organizers have carefully been watching the situation over the past weeks, with full attention for the health and safety of all presenters, exhibitors and attendees, and have explored all options to maintain the event as planned. The current situation with increasing travel restrictions and cancellations, however, no longer makes it possible to guarantee the program and the quality expected from DATE.
Therefore, it has been decided to organize DATE 2020 as a virtual event in the coming weeks instead of the physical event that was planned in Grenoble from March 9 to 13, 2020.
To implement this, the following actions will be taken:
All registered attendees will receive more information through e-mail in the next few days.
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The virtual University Booth of DATE 2020 is available here.
The University Booth is organised during DATE and will be located in the exhibition area at booth 11. All demonstrations will take place from Tuesday, March 10 to Thursday, March 12, 2020 during DATE. Universities and public research institutes have been invited to submit hardware or software demonstrators.
The University Booth programme is composed of 42 demonstrations from 11 countries, presenting software and hardware solutions. The programme is organised in 11 sessions of 2 or 2.5 h duration and will cover the topics:
The University Booth at DATE 2020 invites you to find out more about the latest trends in software and hardware from the international research community.
Most demonstrators will be shown more than once, giving visitors more flexibility to come to the booth and find out about the latest innovations.
We are sure that the demonstrators will give an attractive supplement to the DATE conference program and exhibition. We would like to thank all contributors to this programme.
More information is available online at https://www.date-conference.com/exhibition/university-booth. The University Booth programme is included in the conference booklet and available online at https://www.date-conference.com/exhibition/university-booth/programme. The following demonstrators will be presented at the University Booth.
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This page describes the guidelines to prepare and present audio-visual materials at DATE. Please read all instructions carefully and follow them strictly to maintain the highest possible standards. Even experienced speakers should read the following paragraphs, as they cover several problems that have arisen over the years.
DATE will provide a centralised presentation management system for all speakers of the main conference. You will not be allowed to use your own laptop for presentation on-site – no exceptions.
To enable the A/V staff to handle the technical aspects in an efficient way, all presentations should be prepared according to the "General Instructions for Preparing A/V Material". It is essential that the correct format is used.
Please bring your presentation file with you (CD/DVD/Memory Stick) to the conference and submit it to the presentations server at the A/V Office.
Before the conference, you can upload your presentation by using the web-based upload service at https://date.t-e-m.de. The correct file name is set automatically by the server. The access data for the upload service will be sent to the main contributing author in due time. The upload service will close on 25 February 2020, 23:59:59 CET.
Preview computer systems, identical in software and hardware to the ones used for presentation, will be available in the Audio/Video Office at the conference. This room can be used during below-mentioned times of the DATE 2020 week for presentation concerns. Since this facility will be shared between multiple presenters, its use can be limited.
| Monday | 1300 – 1900 |
| Tuesday | 0730 – 1900 |
| Wednesday | 0730 – 1800 |
| Thursday | 0730 – 1730 |
All presenters are required to meet with the local conference Audio/Video staff at least two hours before the beginning of their session to check their presentation at one of the conference computers. However, it is strongly recommended to do so the day before the session if possible.
The facilities at the A/V Office will provide the possibility of:
Please submit your presentation to the A/V Office via one of the following media:
Save all files associated with your presentation (PowerPoint file, movie/video files etc.) to one folder/location. We recommend to save videos and graphics and pictures separately on your storage medium. In case of problems, we can re-insert the originals.
In the event that you have more than one presentation during the conference, save the different presentations in different folders and name them clearly to avoid any on-site misunderstandings and problems.
Always make a backup copy of your presentations and all associated files and save them on a separate portable medium by yourself.
Conference staff will transfer your presentation from the A/V Office to the corresponding session rooms. You will easily find your presentation on the laptop installed at the lectern in your session room.
Each session room is equipped with:
You can control/move slides during your presentation on your own (by remote control – please kindly check this in the Speaker Preview Room in advance).
Kindly be at the session room at least 20 minutes before the session starts to meet the chair and familiarise yourself with the technical and other equipment.
Using your own laptop for presentation is not possible.
During your presentation you should keep in mind your time limit. The session moderator will stop your presentation if it takes more than your allocated time slot.
There will be a speaker’s breakfast in the morning of your presentation. It will be located in the ground level of the Alpes Congrès Building, and it will start at 7:30 a.m. Attending the speaker's breakfast at the morning of your presentation is mandatory in order to get all final instructions. A sign with the session number will point to your table.
When preparing your AV material, keep the time limit for your presentation in mind. To make your visual presentation a success, it needs to be well planned to clearly point out the important results of your research. The audience will appreciate your talk only if your material is visible and legible. They will remember your talk far better and read your paper if you can manage to communicate at least two important facts within your presentation timeslot. Please consider that the audience will need at least a minute to understand each technical slide.
The first slide should contain the title of your paper and the author names, your affiliations and your company, university or funding logo (if applicable). This will be the only page where logos are permitted.
Keep your material simple and uncluttered. Program listings and very long equations should be avoided. Tables should be represented graphically, wherever possible. Do not use the valuable space on your slides for large company logos and other elements that do not help in motivation or understanding your work. Duplicates of slides should only be produced in case the same information is needed twice.
Please use Microsoft PowerPoint 97-2016 (*.ppt/*pptx), OpenOffice / LibreOffice 1.0 – 6.0, PREZI or Adobe PDF to guarantee your presentation will open successfully on an on-site PC.
All slides must use landscape format with 16:9 aspect ratio.
Please limit the file size to less than 25 MB (except video content) to minimise problems with storage and access speed that can result in a distorted or incomplete presentation.
To speed up your start, we provide a PowerPoint template presentation. You are encouraged to use this template to prepare your presentation. Press here to download the PowerPoint file.
Mac users: please convert your file to PowerPoint format or PDF before you leave for the conference. Be aware that PowerPoint Mac-to-PC conversions can lead to unexpected results, especially with fonts, certain formats of embedded graphics, and special characters (ASCII characters 128 to 255). To avoid questions of PowerPoint compatibility, please embed all used fonts, convert them to vectors or use only compatible fonts (e. g. Arial, Courier New, Lucida Sans, Times New Roman, Verdana).
Because of the many different video formats, support cannot be provided for embedded videos in your presentation; please test your presentation with the on-site PC several hours before your presentation. Generally, the WMV and MPEG-4 format should work without difficulties.
Movies or videos that require additional reading or projection equipment (e.g. VHS cassettes, Video-DVDs) will not be accepted.
Audio is supported.
Only fonts which are included in the basic installation of MS-Windows 10 will be available. Use of other fonts not included in Windows can cause a wrong layout/style of your presentation (Suggested fonts: Arial, Tahoma). If you use different fonts, these must be embedded into your presentation.
Please use high contrast lettering and fonts with a minimum size of 16 pt and high contrast layouts like light text on dark colours.
Please make sure that also index expressions are clearly visible and use an appropriate font size.
Colour should be used carefully and colour combinations resulting in a low contrast (e.g. dark blue on black) should be avoided. Be aware that the contrast of your computer monitor is much higher than that of a projector in a partly lit room
Try to use only colours that convert for black and white printing. The distinction between blue and black for text and thin lines is especially weak. Red filled-in objects (circles, rectangles, etc.) with white text are well-suited for highlighting important text.
The main task of a session chair is to run the session. All speakers have been advised to get in contact with you before the session – please check that all of them are present before your session starts. If one of the speakers is missing, leave the presentation slot empty to be on schedule. Within your session, please introduce the speakers and keep track of the time limits (indicate to the speaker when it is time to stop). Please also manage the question and answer procedure after each talk (long dialogues have to be done off-line). If there are Interactive Presentations assigned to your session, please provide a one-minute time slot to each of them at the end of the session. After your session, please fill in the session evaluation form and return it to the conference registration desk.
The main task of a session co-chair is to support the session moderator and to handle unexpected situations. Please estimate the number of attendees (required for the evaluation form). You are requested to handle unexpected noise (talk to security people), A/V problems (talk to A/V people / technicians) and look for missing speakers. Please replace the missing session chair in case he is not present due to unexpected circumstances.
For further information, please have a look at the guidelines for your appropriate session below.
If you are also the chair or co-chair of your session, please have a look at the "Further Instructions for Session Chairs and Co-Chairs".
The presentation timeslot is 25+5 minutes for long and 13+2 minutes for short presentations, including the +time for questions. Please consider that the audience will need at least a minute to understand each technical slide. Therefore, you should prepare 15 to 20 slides for long and 10 to 15 slides for short presentations.
IP authors have two time slots for presentation. One first time slot is scheduled at the end of a regular session for a short advertisement of the poster presentation being scheduled in the following IP session. The timeslot for your advertisement presentation is only one minute. You are allowed to show at most two slides (cover page included).
The second time slot is characterised by an oral explanation given to interested audience during the interactive presentation sessions. Each IP session runs on a 30 minutes’ timeslot and will be supported by a compulsory poster according to the guidelines indicated below. Therefore, please be in the IP area at least 15 minutes before the session starts to correctly mount the poster. Please also take care of removing it at latest 60 minutes before the next IP session. Posters from previous sessions will be removed and disposed. You do not have to prepare presentation slides for this time slot as there will be no table or power socket nearby the poster wall.
Finally, remember that the best IP award selection committee will check the quality of the presentation and of the answers during the IP sessions to make its decision.
IP authors are kindly asked to prepare posters in DIN A0 portrait format (841x1189 mm / 33.11x46.81 in) and bring the printed poster to the conference. There is no poster printing service on-site. The poster will be exhibited in the IP session area on the poster walls labelled with the corresponding IP number. Blu-Tack/Pins will be provided. Posters made as mosaic of A4 or letter papers are discouraged.
The centralised presentation management system will NOT be used for Monday Tutorials and presentations will be handled individually by each Tutorial Organiser. Please contact your Tutorial Organiser to get information on the organisation of your presentation.
The centralised presentation management system will NOT be used for Friday Workshops and presentations will be handled individually by each Workshop Organiser. Please contact your Workshop Organiser to get information on the organisation of your presentation.
For more information please contact:
Conference Organization - Conference Manager
Eva Smejkal, K.I.T. Group GmbH Dresden, DE
datekitdresden [dot] de (date[at]kitdresden[dot]de)
phone: +49 351 65573-133
fax: +49 351 65573-299
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DATE 2020 Advance Programme for download
Keynotes: https://www.date-conference.com/keynotes
Monday Tutorials: https://www.date-conference.com/conference/monday-tutorials
PhD Forum: https://www.date-conference.com/fringe-meeting-fm01
Conference Programme: https://www.date-conference.com/programme
Special Days, Executive & Special Sessions: https://www.date-conference.com/special
Exhibition Theatre: https://www.date-conference.com/exhibition/exhibition-theatre
Friday Workshops: https://www.date-conference.com/conference/friday-workshops
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For the 23rd year in a row, DATE has prepared an exciting technical programme. With the help of the 328 members of the Technical Programme Committee, who carried out 3014 reviews (mostly four reviews per submission), 196 papers (26%) were finally selected for regular presentation and 82 additional ones (cumulatively 37%, including all papers) for interactive presentation.
DATE 2020 programme will include five keynote talks. Two visionary talks will be given during the opening ceremony: one from Philippe Magarshack, Corporate Vice President at ST Microelectronics, and one from Luca Benini, chair of digital Circuits and Systems at ETH Zurich and Professor at University of Bologna. Moreover, three luncheon keynotes will inspire the attendees: on Tuesday, Catherine Schumann from Oak Ridge National Laboratory will talk about neuromorphic computing; on Wednesday, Jim Tung will present Mathworks’ vision on how to leverage Embedded Intelligence in Industry; on Thursday, Joachim Schultze from DZNE will talk about bottlenecks and challenges for HPC in medicinal and genomics research.
The conference programme includes several executive and hot-topic sessions, addressing Memories for Emerging Applications, Architectures for Emerging Technologies (Quantum Computing, Edge Computing, Neural Algorithms, In-Memory Computing, Bio-Inspired Adaptive Hardware), Hardware Security, 3D Integration and Logic Reasoning for Functional ECO.
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