Ensuring vehicle electronics reliability levels as mandated by the ISO 26262 standard requires periodic testing during functional operation. The Tessent MissionMode architecture provides system-level access to all on-chip test resources for key-on, key-off and runtime testing. This presentation will walk through the flow for implementing a chip-level architecture incorporating the MissionMode solution integrated with both logic BIST and Memory BIST capabilities.

As part of the Mont Blanc 2020, European scalable, modular and power efficient HPC processor, ATOS designs and implement a NoC which includes NoC Xpoints, Protocol agents and system cache.

Our Network on Chip (NoC) is based on basic Xpoint modules which are connected to each other to make a scalable NoC. Each Xpoint module has :

• 4 internal CHI Interface (1 per direction) where all the Xpoint modules are connected to
• 2 End Points CHI Interface which are the entry/exit points of IPs on the System on Chip (Soc)

A CHI interface contains 4 channels interfaces: Request, Data, Snoop and Response. Each channel is fully configurable in each direction and is implemented with Configurable System Verilog Interface. This makes a lot of parameters to handle as we plan to implement an 8x8 NoC which includes 64 Xpoint modules with corresponding parameters set accordingly.

Defacto STAR tool is used to efficiently:

• instantiate all the Xpoint modules with corresponding parameters
• connect all the channels with corresponding System Verilog Interface
• connect the Error, status and configuration interfaces
• connect Protocol Agent on End Point interface (internally)
• create NoC entity.

The main benefits to choose Defacto STAR is

• NoC configuration change and RTL generation in 15 s
• No need to develop our own tools

NoC module will then be integrated at SoC level and connected to IPs delivered by Third-parties. We also use Defacto STAR tool to generate the SoC RTL and associated Testbench.

The increasing complexity of system on chips (SoCs) combined with a new generation of designs that combine multiple chips in a single package (Sip) is creating new challenges in the design of IC packages, printed circuit boards (PCBs) and integrated circuits (ICs). The process typically involves three independent design processes – chip, package and PCB – carried out with point tools whose interface requires time-consuming manual processes that are error-prone and limit the potential for reuse. This challenge is being addressed by a new integrated 3D chip/package/board co-design environment that makes it possible to take quick decision of the best SiP implementation by considering the system-level impact of each design decision, especially for optimizing. The new co-design approach enables netlist management to follow up design modification including die partitioning and seamless electrical characteristic verification during the design. The end result is higher performance and improved quality for smart systems, MEMS and IoT applications.