Opening Session

Alberto Bosio (INL, France), Said Hamdioui (TUDelft, The Netherlands), Elena-Ioana Vatajelu (TIMA, France)

Keynote Address

To be announced

Panelists (preliminary list):

• Henri-Pierre Charles (CEA-LETI, FR)
• Shahar Kvatinsky (Technion, Israel)
• Alexandre Levisse (EPFL, CH)
• Georgios Sirakoulis (University of Thrace, GR)

Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks 

Gokul Krishnan*, Sumit K. Mandal*, Chaitali Chakrabarti, Jae-sun Seo, Umit Y. Ogras, Yu Cao (School of Electrical, Computer and Energy Engineering, Arizona State University)

Conversion-in-Memory Using Floating-Gate Memristive Neural Networks

Loai Danial, Shahar Kvatinsky (Viterbi Faculty of Electrical Engineering, Technion - Israel Institute of Technology)

Exact Stochastic Computing Multiplication in Memristive Memory

Mohsen Riahi Alam, M. Hassan Najafi (University of Louisiana at Lafayette, Louisiana, USA), Nima TaheriNejad (TU Wien, Vienna, Austria)

Efficient 8-bit matrix multiplication on Computational SRAM architecture

Mambu Kévin, Charles Henri-Pierre, Kooli Maha (Université Grenoble Alpes, CEA LIST, F-38000 Grenoble, France)

​​​​​​Simulation and experimental characterization of memristive crossbar arrays for computation-in-memory

J. Mohr, C. Bengel, M. Abu, S.Hamdioui, D.J. Wouters, S. Menzel, R. Waser

Sensing and Processing in Memristive Arrays

Saurabh Khandelwal (School of ECM, Oxford Brookes University, Oxford), Shahar Kvatinsky (Viterbi Faculty of Electrical Engg., Technion - Israel Institute of Technology), Marco Ottavi, Eugenio Martinelli (Electronic Engg., University of Rome “Tor Vergata”, Rome, Italy), Abusaleh Jabir (School of ECM, Oxford Brookes University, Oxford)

Exploration of a Scalable Vector-Tile-based In-Memory Computing Architecture

Roman Gauchi, Valentin Egloff, Maha Kooli, Jean-Philippe Noel, Bastien Giraud, Pascal Vivet (Université Grenoble Alpes, CEA LIST, Grenoble, France), Subhasish Mitra (Stanford University, Palo Alto, CA, USA), Henri-Pierre Charles (Université Grenoble Alpes, CEA LIST, Grenoble, France)

Reuse-aware architecture and synthesis flow for NVM-based FPGAs

João Paulo Cardoso de Lima, Rafael Fão de Moura, Luigi Carro (Departamento de Informática Aplicada Instituto de Informática - UFRGS)

Toward CIM architecture with a new tile-level simulator

Mahdi Zahedi, Stephan Wong, Said Hamdioui (Computer Engineering Laboratory, Delft University of Technology, The Netherlands)

Control, instruction set for memristor-based CIM